1. Field of the Invention
The present invention relates to apparatus and a method for determining the sum of first and second optical binary words, each word having a number of optical bit slots.
2. Description of Related Art
In the field of all optical processing, optical signal streams are used for data processing applications. These optical streams consist of an optical pulse train that is divided into a series of bit slots. Each bit slot, which has a predetermined length within the pulse train, represents a single bit of data, with the presence or absence of an optical pulse within a bit slot representing complementary logical states. Thus, for example, the presence of an pulse may represent a binary xe2x80x9c1xe2x80x9d, whilst the absence of an optical pulse may represent a binary xe2x80x9c0xe2x80x9d, or vice versa. In this specification, therefore, we use the terminology xe2x80x9coptical binary wordxe2x80x9d to mean a binary word represented optically in this manner.
One of the basic optical processing applications which is required is the ability to generate the binary sum of two optical binary words each word consisting of a number of bit slots.
According to a first aspect of the present invention, we provide apparatus for determining the sum of first and second optical binary words, each word having L optical bit slots, each bit slot representing a respective one of first and second logical states, the apparatus comprising a first optical logic gate which generates a first combination word representing a first logical combination of binary words applied thereto, a second optical logic gate which generates a second combination word representing a second logical combination of binary words applied thereto, offsetting means for offsetting the first and second combination words by one bit slot with respect to each other to generate first and second offset combination words, and means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates which respectively generate first and second combination words representing the first and second logical combination of the binary words applied thereto, wherein the first and second offset combination words initially comprise the first and second binary words, the binary sum being given by the first combination word then each bit slot of the second combination word has the same logical state.
According to a second aspect of the present invention we provide a method for determining the sum of first and second optical binary words, each word having L optical bit slots, each bit slot representing a respective one of first and second logical states, the method comprising the steps of:
1) generating a first combination word representing a first logical combination of first and second offset combination words;
2) generating a second combination word representing a second logical combination of first and second offset combination words;
3) generating the first and second offset combination words by offsetting the first combination word by one bit slot with respect to the second combination word;
4) continuously repeating steps 1), 2) and 3) until each bit slot of the second combination word has the same logical state, wherein the first and second offset combination words initially comprise the first and second binary words, the binary sum being given by the first combination word when each bit slot of the second combination word has the same logical state.
Exemplary embodiments of an apparatus and a method of the present invention generate the sum of first and second optical binary words. This is achieved by generating first and second combination words representing first and second logical combinations of the optical binary words, using first and second optical logic gates. These optical combination words are then offset with respect to each other and recombined to generate further combination words. By repeating this process until each bit slot of the second combination word has the same logical state, the binary sum of the first and second binary words can be determined.
Typically the first and second logic gates have first and second inputs for receiving the binary words to be combined, although a single input could be utilised with the binary words to be combined being applied consecutively.
Preferably the means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates comprises a connection from the output of the first logic gate to the second inputs of the first and second logic gates, and a connection from the output of the second logic gate to the first inputs of the first and second logic gates. This is effectively a feedback system, with the combination word generated at the output of each logic gate being fed back to an input of both logic gates.
Alternatively however a feed forward system can be employed in which the means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates comprises N first and second optical logic gate pairs, each first and second optical logic gate pair comprising a first optical logic gate which generates a first combination word representing a first logical combination of binary words applied thereto, a second optical logic gate which generates a second combination word representing a second logical combination of binary words applied thereto, and offsetting means for offsetting the first and second combination words by one bit slot with respect to each other to generate first and second offset combination words, wherein the offsetting means is coupled to the downstream first and second optical logic gate pair such that the generated first and second offset combination words are applied to the first and second logic gates of the downstream first and second optical logic gate pair.
In the feedback system the offsetting means typically comprises an L bit slot delay line coupled to the output of the first optical logic gate and either an L+1 or an Lxe2x88x921 bit slot delay line coupled to the output of the second optical logic gate. Whilst any suitable method of introducing a one bit slot delay may be used, it is very difficult to introduce single bit slot delays at high bit rates. Accordingly, it is preferable to use L and either L+1 or Lxe2x88x921 bit delays allowing a one bit slot offset to be generated between the relevant optical binary words. Furthermore by using L and L+1 and Lxe2x88x921 bit slot delays, the output combination words can subsequently be fed back to the inputs of the logic gates without interfering with the previously input words.
The use of the L+1 or Lxe2x88x921 bit slot delay will depend on the format of the optical binary words. Thus if the first bit slot of the optical binary word represents the least significant bit of the binary numbers to be added, then the L+1 bit slot delay is used. On the other hand, if the first bit slot represents the most significant bit then the Lxe2x88x921 bit slot delay is used.
For ease of discussion the remainder of the specification will discuss examples in which the first bit slot represents the least significant bit of the binary numbers to be added, unless otherwise stated. Accordingly, the use of the L+1 bit slot delay will be assumed, although it will be appreciated that for a different optical binary word format the Lxe2x88x921 bit slot delay would be used.
Typically, in the feedback system, the connection from the first logic gate to the second inputs of the first and second logic gates comprises the L bit slot delay line, and wherein the connection from the output of the second logic gate to the first inputs of the first and second logic gates comprises either the L+1 or the Lxe2x88x921 bit slot delay line, although additional connections may be employed.
Preferably the feedback apparatus further comprises an optical combiner, the optical combiner having a first combiner input coupled to the L+1 bit slot delay line, a second combiner input which receives the first and second optical binary words, and a combiner output coupled to the first inputs of the first and second logic gates.
Whilst the optical combiner is not required for calculating the sum of two optical binary words, the presence of the combiner does not effect the operation of the circuit. Furthermore, as will be explained below, it is sometimes desirable to input more than two optical words to the circuit. In this case, the combiner is provided to prevent interferometric mixing of the optical word supplied to the circuit with the optical pulses already present in the circuit.
The optical combiner operates by combining bit slots received at the first and second inputs such that if the bit slots have identical logical states, the combiner output generates a bit slot having the first logical state and if the bit slots have different logical states, the combiner output generates a bit slot having the second logical state. In use, this allows the first and second words to be supplied in sequence to the second combiner input such that the first and second words are supplied respectively to the first and second inputs of the first and second optical logic gates.
In the feedforward system, the offsetting means typically comprises an M bit slot delay line which couples the first logic gate to the second gate inputs of the downstream first and second logic gate pair, and an M+1 bit slot delay line which couples the second logic gate to the first gate inputs of the downstream first and second logic pair such that the transfer of the first combination word is delayed by one bit slot with respect to the transfer of the second combination word. Whilst any suitable method of introducing a one bit slot delay may be used, it is very difficult to introduce single bit slot delays at high bit rates. Accordingly, it is preferable to use M and M+1 bit delays, for M greater than 1, allowing a one bit slot offset to be generated between the relevant optical binary words.
Again, as described with respect to the feed forward system an Mxe2x88x921 bit slot delay line could be used instead of the M+1 bit slot delay line if the format of the optical binary words has the most significant bit in the first bit slot.
Preferably, the Nth first and second logic gate pair comprises feedback apparatus with the M bit slot delay line of the Nth first and second optical logic gate pair being constituted by the L bit slot delay line and the M+1 bit slot delay line of the Nth first and second optical logic gate pair being constituted by the L+1 bit slot delay line. Such an arrangement combines the advantages of both the feedback and the feedforward aspects of the present invention.
Preferably, each first logic gate comprises an XOR gate and wherein each second logic gate comprises an AND gate. It will be realized however that the invention could be implemented using complementary logic, in which case alternative logic gates, such as XNOR and NAND gates, would be used.
Typically each optical AND gate comprises an all optical non-linear gate, wherein the application of a bit slot having the second logical state to the first input selectively switches a connection between the second input and the output for a time interval corresponding to a single bit slot so as to transfer a single bit slot from the second input to the output, whereby a bit slot is generated at the output representing the logical AND of the bit slots received by the first and second inputs. This provides a simple means for combining optical words to generate the logical AND of the two words.
Typically each optical XOR gate comprises an optical combiner, the optical combiner comprising a first combiner input coupled to the first input of the XOR gate; a second combiner input coupled to the second input of the XOR gate; and, a combiner output, wherein if the bit slots received at the first and second combiner inputs have identical logical states, a bit slot having the first logical state is generated at the combiner output and wherein if the bit slots received at the first and second inputs have different logical states, a bit slot having the second logical state is generated at the combiner output. This apparatus provides a simple way of generating the logical XOR of first and second binary words.
Typically the XOR gate further comprises a source which generates a stream of bit slots having the second logical state and, an all-optical non-linear gate, the non-linear gate comprising a gate input coupled to the source, a gate output coupled to the XOR gate output and, a gate switching input coupled to the optical combiner output, wherein the application of a bit slot having the second logical state to the gate switching input selectively switches a connection between the gate input and the gate output, for a time interval corresponding to a single bit slot, so as to transfer a single bit slot from the gate input to the gate output. This ensures the optical quality of the optical word representing the logical XOR of the combined words is of good quality and is in the correct format for use by the rest of the circuit.
Typically the second logical state is defined by a bit slot containing a single optical pulse, although this depends on the specific implementation of the circuit and it is therefore evident that a bit slot containing a single optical pulse may define the first logical state.
Typically the first combination word represents the binary sum when each bit slot of the second binary word has the first logical state, although again this depends on the specific implementation of the circuit.
According to a third aspect of the present invention, we provide a method of counting a number of binary words, each binary word having L bit slots, the first or the Lth bit slot having a second logical state, the remaining Lxe2x88x921 bit slots having a first logical state, the method comprising the steps of:
1) generating a first combination word representing a first logical combination of first and third combination binary words;
2) generating a second combination word representing a second logical combination of first and third combination binary words;
3) generating first and second offset combination words by offsetting the first combination word by one bit slot with respect to the second combination word;
4) generating the third combination word by combining the offset second combination word with a further binary word;
5) continuously repeating steps 1), 2) 3) and 4) until the number of binary words have been combined and each bit slot of the second combination word has the same logical state, wherein each of the first and second offset combination words initially comprise one of the number of binary words, the count of the number of binary words being given by the first combination word when each bit slot of the second combination word has the same logical state.
Typically, in either method of the invention the first logical combination comprises an XOR combination and the second logical combination comprises an AND combination. It will be realized however that the methods could be implemented using complementary logic, in which case alternative logical combinations would be used.
Typically the methods are continuously repeated until each bit slot of the second combination word has the second logical state, although this will depend on the implementation of the methods.
Preferably, the second logical state is defined by a bit slot containing a single optical pulse, although a bit slot containing a single optical pulse may define the first logical state.
In the case when the first bit slot has the second logical state, then preferably the first and second offset combination words are generated by temporarily storing the first combination word for a time interval corresponding to M bit slots and temporarily storing the second combination word for a time interval corresponding M+1 bit slots. In contrast, if the Lth bit slot has the second logical state, then preferably the second combination word is stored for a time interval corresponding to Mxe2x88x921 bit slots. As explained above with respect to the feed forward system, the use of the M bit slot and either the M+1 or Mxe2x88x921 bit slot delays overcomes the problems associated with introducing single bit slot delays at high bit rates.
The method according to the second aspect of the invention is preferably carried out utilizing apparatus according to the first aspect of the invention.
Typically, the method according to the third aspect of the invention may be carried out utilizing apparatus according to the first aspect of the invention when the apparatus further comprises the optical combiner, as mentioned above.